1. Field of the Invention
The present invention relates to semiconductor packaging and more particularly, to a method and apparatus for providing a high-performance, low-CTE (coefficient of thermal expansion), low-cost substrate, to interface with a low-K dielectric and integrated circuit without cracking.
2. Description of the Related Art
Semiconductor technology may be characterized as a quest to place more transistors on less space to achieve greater speed and performance. As integrated circuits and other semiconductor devices become faster, operating frequencies (i.e. clock speed in a microprocessor) also increase. At the same time, engineers and developers also strive to construct semiconductor devices that are more compact, therefore the distances between the conductive lines within the semiconductor device are being decreased accordingly.
The combination of higher operating frequencies and more compact circuitry results in an increased level of crosstalk, which is a disturbance caused by electromagnetic interference between the conductive lines. This interference may take the form of electromagnetic (inductive) or electrostatic (capacitive) coupling between the conductors. Crosstalk causes signal disruption in adjacent circuits and can cause the signals to be confused and cross over each other, all of which slows the operation of the semiconductor device. Therefore, it is extremely important to have dielectric layers that effectively insulate conductive lines against crosstalk.
In general, the amount of crosstalking between two conductive lines is proportional to the dielectric properties of the material insulating the lines. These properties may be measured to form a dielectric constant (K). The lower the dielectric constant, the better the insulator the material is. Integrated circuits conventionally include dielectric layers between conductive lines, typically comprised of silicon dioxide (SiO2), which has a dielectric constant of about 4.0.
As a consequence of the increasing line densities and operating frequencies in integrated circuits, SiO2 dielectric layers often do not have a low enough dielectric constant to provide adequate insulation. Therefore, in an effort to reduce crosstalk in integrated circuits, developers and engineers have attempted to develop insulating materials that have a much lower dielectric constant. A number of dielectric layers comprising organic materials, which are sometimes referred to as being “low-K” and “ultra low-K” dielectrics, have been developed. However, unlike conventional SiO2 dielectric layers, low-K and ultra low-K dielectric materials often pose difficult implementation problems due to weak mechanical strength and low CTE.
A chip package typically includes an IC (e.g., in a chip die) connected to a chip carrier substrate, which interfaces the die to a motherboard socket. The main problem with using ultra low-K insulation in a chip package is that ultra low-K materials are brittle and weak compared to conventional SiO2. Organic resin in the chip carrier (typically BT (bismaleimide-triazine), has a high coefficient of thermal expansion (CTE) of about 17 parts per million per degrees Celsius (PPM/° C.). A chip carrier with an ultra low-K dielectric typically has a CTE of only about 3 PPM/° C., there would be a significant CTE mismatch resulting from contact between an ultra low-K chip carrier substrate and a chip die.
The mismatch would apply a great deal of stress on the low-K dielectric layers of chip die. Since this material is extremely weak and brittle, there is a risk of dielectric cracking and delamination due to temperature cycling during fabrication processing and normal usage of the device. In contrast, when conventional SiO2 dielectric layers are used, the chip die is strong enough to prevent problems that might result from the CTE mismatch. The introduction of an ultra low-K dielectric material poses a significant challenge on packaging technology to reduce the additional stress.
One conventional solution to the CTE mismatch problem is to use a chip package where the chip carrier substrate comprises a ceramic instead of an organic material. A ceramic substrate typically has a CTE of only about 6 to about 7 PPM/° C., resulting in a much lower CTE mismatch. Due to the strength of the chip die and the low CTE mismatch, no cracking will result. Unfortunately, ceramic dielectric layers have a much higher K than organic dielectric layers and will not be an adequate insulator in future generations of chip carrier substrates. Another disadvantage of using ceramics is that the conductors are formed by screen printing instead of photolithography. Therefore, feature sizes will not be as small as in conventional photolithographic methods, limiting the ability of the technology to keep up with improvements in silicon processing.
In addition, ceramic substrates are expensive when compared to organic substrates. Because feature sizes are larger in ceramic substrates, about 12 to about 15 ceramic layers (approximately 2 millimeters thick) must be used to accommodate the large number of input/output lines from the chip die to the chip carrier substrate. Furthermore, such a structure requires accommodation for land-side capacitors.
There are ceramic/organic substrates available in the market today. These are typically very expensive modules that integrate conventional ceramic technology with multilayer polyimide dielectric coatings. The dielectric coatings are either screen coated or spun on making the process very expensive and time consuming. Some existing ceramic substrates include a cavity on the top side of the substrate to accommodate the chip.
In view of the foregoing, there is a need for a method and apparatus to provide a high performance/low cost substrate, which is able to interface with a chip die without cracking. There is also a need for a method and apparatus to more easily accommodate capacitors without interfering with either a socket or surface mount technology (SMT) package interface to a motherboard.